PCB Design and Bring-Up

A review and first-power workflow centered on current paths, test access, and recoverable failures.

Hardware ยท Board Design

A PCB is electromagnetic, thermal, mechanical, and manufacturing hardware. The schematic defines intended connectivity. Placement, stackup, and routing determine much of the circuit that gets built.

Define the board before capture

Write down the constraints that will drive the design:

  • power sources, rails, sequencing, peak load, and fault-energy limits,
  • interfaces, voltage domains, edge rates, and connector pinouts,
  • mechanical outline, mounting, enclosure, and approved stackup,
  • operating environment and thermal boundaries,
  • EMC and regulatory targets,
  • programming, debug, calibration, and production-test access,
  • assembly process, expected volume, bill of materials (BOM), and component availability,
  • safe states and fault-containment behavior.

This turns schematic review into a check against explicit requirements instead of visual inspection alone.

Quantify the power path

Estimate the complete source-to-load path, including both copper directions, connectors, protection, switches, and current-sense elements:

\[V_{\text{drop}} = IR\] \[P_{\text{loss}} = I^2R\]

For a 2 A load and $80\ \text{m}\Omega$ total path resistance:

\[V_{\text{drop}} = 160\ \text{mV}, \qquad P_{\text{loss}} = 320\ \text{mW}\]

Compare the remaining load voltage against its minimum input requirement during startup and peak load. Measure resistance or voltage drop on the assembled board when connector, via, and plane contributions are difficult to estimate accurately.

Illustrative first-power plan

The limits below describe a hypothetical 5 V input, 3.3 V logic board. They show the level of specificity a bring-up plan needs. They are not reusable limits.

Checkpoint Setup Expected result Stop condition
Input resistance board unpowered, loads discharged stable value consistent with populated loads falling resistance, near-short, or disagreement with known-good unit
Initial input current 5.0 V supply, 120 mA limit, processor held in reset 45 to 75 mA after startup transient current limit persists or current rises with time
Logic rail DMM at farthest 3.3 V load 3.234 to 3.366 V outside static tolerance
Rail transient 20 MHz-limited scope at load pins less than 30 mV peak-to-peak in defined idle mode oscillation, droop, or repeated startup
Reset scope at receiver pin one clean transition after rails are valid chatter, slow threshold crossing, or early release
Minimal firmware debugger plus serial console device ID, one GPIO transition, one versioned banner full application needed to observe life

Record the actual measured range from the first known-good units. Replace estimated current and resistance windows with revision-specific production limits once enough data exists.

Review the schematic by function

  • Give every pin a deliberate state. Distinguish recommended operating limits from absolute maximum ratings.
  • Trace power, reset, clock, boot, debug, and programming paths from source to load.
  • Size pull resistors from leakage, current, rise time, and required default behavior.
  • Treat decoupling as a current-loop problem. A capacitor value without placement and connection geometry is incomplete.
  • Give protection components a defined current path, clamp target, and energy rating.
  • Review connector ground returns, hot-plug behavior, ESD exposure, and misconnection cases.
  • Include tolerance, drift, and derating where they affect a requirement.

Place and route in dependency order

  1. Lock the outline, mounting, connectors, keepouts, and stackup.
  2. Place power conversion and high-energy current paths.
  3. Place clocks, converters, RF, and precision analog around their critical loops.
  4. Preserve continuous reference planes under fast signals. Do not route a signal across a plane gap and force its return current around the gap.
  5. Route controlled-impedance and timing-critical nets using the fabricator-approved stackup.
  6. Route power for transient current, voltage drop, and temperature rise, not only average current.
  7. Add test access, fiducials, polarity marks, and assembly notes.
  8. Review return paths and current loops separately from the signal traces.

Use a pre-fabrication release gate

A clean design-rule check is necessary but not sufficient. Before ordering, freeze the revision and review the exact manufacturing package rather than only the editor view.

Release item Required evidence Common escape
schematic and PCB parity annotated electrical-rules check (ERC) and design-rules check (DRC) reports, all exclusions justified stale netlist, ignored unconnected pad, unfilled zone
stackup and rules fabricator-approved materials, copper, impedance geometry, and tolerances routing against a preliminary stackup
fabrication data plotted layers, drill files, board outline, impedance notes, and readme inspected in an independent viewer missing layer, wrong origin, obsolete plot
assembly data BOM, approved substitutions, centroid data, polarity, pin-one, and do-not-populate (DNP) state BOM and placement outputs disagree
mechanical fit STEP or enclosure review plus connector, fastener, and keepout checks model origin or component-height error
power-off behavior back-power, hot-plug, discharge, and unpowered-interface paths reviewed rail energized through an I/O or protection diode

Archive the release reports and generated outputs with the source revision. KiCad can run parity-aware DRC and generate fabrication outputs, but the release decision still requires review of warnings, exclusions, vendor constraints, and the exported files themselves.

Design for bring-up

Provide access to:

  • each rail and major ground domain,
  • reset, boot mode, programming, and debug,
  • critical clocks and a serial console,
  • current measurement or removable rail isolation,
  • conducted RF paths where appropriate,
  • fixture alignment and low-inductance fixture ground.

Test pads are electrical structures. On sensitive nodes they can add capacitance, leakage, coupling, or a transmission-line stub. Include them in the model and layout review.

First-power sequence

  1. Record the board revision and inspect orientation, polarity, solder bridges, unpopulated parts, and rework under magnification.
  2. Measure resistance from every rail to ground. Compare against a known-good board or expected load when possible.
  3. Power from a current-limited source. Hold processors and high-current loads inactive if the design permits it.
  4. Measure rail value, ripple, sequence, and total current at the board, not only at the supply.
  5. Confirm reset and clock behavior.
  6. Attach the debugger and read device identity before loading the complete application.
  7. Run minimal firmware with one observable result.
  8. Enable one peripheral or interface at a time.
  9. Add motors, heaters, radios, and other high-current loads last.
  10. Record firmware, configuration, measurements, rework, and anomalies against the board serial number.

Fault isolation

Symptom First checks
Excess current rail resistance, current by rail, current-limit response, thermal image
No debug connection target voltage, reset, clock, SWD or JTAG continuity, boot straps
Random resets rail droop, reset pin, watchdog cause, brownout flags, clock integrity
Bus errors logic levels, pull-ups, timing, addressing, continuity, return path
ADC noise reference, source impedance, grounding, acquisition timing, clock and rail activity
RF desense conducted baseline, digital operating modes, rail spectrum, cable and enclosure currents

Change one variable at a time and preserve the failing configuration until the cause is understood.

Release evidence

  • schematic and layout review records,
  • approved stackup and fabrication notes,
  • assembly drawing, centroid data, and BOM revision,
  • bring-up log and known rework,
  • test procedure, limits, and raw measurements,
  • firmware and configuration identifiers,
  • open deviations with an owner and disposition.

EMC, EMI, and Grounding, Measurement and Instrumentation, RF PCB Layout and Signal Integrity, and Design Verification and Test.

Sources